1. Field of the Invention
The present invention relates to a semiconductor fabrication method. More particularly, the present invention relates to a method of fabricating a transistor.
2. Description of the Related Art
Conventionally, a self-aligned silicide layer, also known as a salicide layer, is formed on a source/drain region, which is located on opposite sides of a gate, so as to decrease the resistance for a transistor.
FIGS. 1A through 1F are schematic, cross-sectional views illustrating a conventional method of fabricating a transistor.
In FIG. 1A, a gate 106 is formed on a substrate 100. The gate 106 comprises a gate oxide layer 102 and a polysilicon layer 104 formed in sequence over the substrate 100. A shallow trench isolation (STI) structure 108 is formed in a portion of the substrate 100.
In FIG. 1B, a light doping step is performed with the gate 106 serving as a mask. A lightly doped drain (LDD) region 110, which has a pocket-doped region, is formed in the substrate 100 on opposite sides of the gate 106.
In FIG. 1C, an oxide layer (not shown) is formed by chemical vapor deposition over the substrate 100 to cover the gate 106. Anisotropic etching is performed to etch the oxide layer. A spacer 112 is formed on a sidewall of the gate 106.
In FIG. 1D, a doping step is performed with the gate 106 and the spacer 112 serving as masks. Arsenic (As) ions are doped into the substrate 100. The arsenic-doping step is performed with a high energy of about 60-80 KeV and a high dosage of about 3E15 atoms/cm.sup.2. A source/drain region 114 is formed in the substrate 100 on opposite sides of the spacer 112.
In FIG. 1E, a titanium layer 116 having a thickness of about 200 angstroms to about 1000 angstroms is formed over the substrate 100 by sputtering.
In FIG. 1F, a thermal step is performed. During the thermal step, the titanium layer 116 reacts with the silicon of the gate 106 and the source/drain region 114 to form silicide layers 118, known as self-aligned silicide layers. A wet etching is performed with a H.sub.2 O.sub.2 solution and a NH.sub.4 OH solution to remove the unreacted titanium layer 116.
In the above-described fabrication process, the source/drain region 114 is formed by doping the arsenic (As) ions with a high energy of about 60-80 KeV and a high dosage of about 3E15 atoms/cm.sup.2. During the high-energy ion bombardment, dislocations are easily formed in the substrate 100 and affect the device performance. In contrast, if the source/drain region 114 is formed by doping arsenic ions having a low energy and a high dosage, dislocations in the substrate 100 can be reduced. However, even though the dislocations can be reduced in this manner, the formation of the silicide layer is partially obstructed by the high-concentration source/drain region 114. This, in turn, decreases the formation of the silicide layer, resulting in an increased resistance. In addition, the drain-induced barrier lowering (DIBL) effect can be reduced by an LDD structure formed with a low doping energy. However, in order to increase the saturated current (I.sub.DSAT) of devices, dosages are increased. In this manner, the resistance for source/drain region 114 is affected.
Moreover, since the thermal step for forming the silicide layer 118 is performed after the formation of the source/drain region 114. In the high-temperature environment, ions in the source/drain region 114 tend to further diffuse. As a result, junction capacitance of the source/drain region 114 is increased, and thus the operation speed is affected. The junction leakage current is increased.